1. Technical Field
This invention relates to the field of phase locked loops and more particularly to high speed phase locked loops (PLLs).
2. Description of the Related Art
A phase locked loop typically has three core components, namely, a phase detector or multiplier, a loop filter and a voltage controlled oscillator (VCO). PLLs can also include a prescaler. For a given technology, a PLL dual modulus prescaler usually sets the upper limit on the maximum operating frequency. Existing PLL architectures and dual-modulus prescaler architectures fail to enable the maximum potential frequency limits of operation for the PLL and prescaler while also maintaining other desirable PLL performance parameters.
A CMOS high-speed PLL would ideally include other characteristics that are not readily achievable with existing technology while operating at a maximum frequency. Namely, such PLL would ideally operate at a low voltage, draw a small current, have minimal phase noise for the PLL and VCO, and further have a small footprint in terms of chip size.
Thus, a need exists for a PLL and a prescaler that can operate at a high frequency and overcome the detriments described above.